1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the formation of small circuit elements, such as a gate electrode of a field effect transistor, on a substrate by sophisticated trim etch techniques requiring advanced masking schemes, wherein the dimensions of the circuit elements are significantly less than the resolution of the involved lithography technique.
2. Description of the Related Art
The trend in recent years to steadily decrease the feature sizes of circuit elements in integrated circuits will continue in the near future, wherein reproducible and robust processes have to be established that allow the formation of a huge number of integrated circuits in a cost-efficient manner. Presently, sophisticated integrated circuits that are available as mass products include elements having dimensions which are well below the optical resolution of the lithography apparatus used for transferring a pattern from a mask into a material layer formed on a substrate. Minimum dimensions of circuit elements are presently 100 nm and less, wherein the wavelength of radiation used for optically transferring patterns from the mask to the substrate surface are in the deep ultraviolet range, for example at 248 nm, and, in recently developed techniques, at approximately 193 nm. In this wavelength range, the absorption of optical transmissive elements, such as lenses, is considerable and will drastically increase with a further reduction of the wavelength. Thus, merely reducing the wavelength of light sources for lithography apparatus is not a straightforward development and may not easily be implemented in mass production of circuit elements having feature sizes of 50 nm and less. Thus advanced trim processes are required so as to obtain the final desired dimension from the minimum dimension that may be achieved with resist features by lithography.
Hence, the total resolution of reliably transferring circuit patterns from a mask to a substrate is determined, on the one hand, by the intrinsic optical resolution of the photolithography apparatus, the characteristics of materials involved in the photolithography patterning process, such as the photoresist and any anti-reflective coatings (ARC) that are provided to minimize deleterious scattering and standing wave effects in the photoresist, and by deposition and etch procedures involved in forming the resist and ARC layers and etching these layers after exposure. In particular, the highly non-linear behavior of the photoresist, in combination with sophisticated ARC layers and lithography mask techniques, allows the formation of resist patterns having dimensions considerably below the intrinsic optical resolution of the photolithography apparatus. Additionally, a further post-lithography trim etch process is applied to further reduce the feature sizes of the resist pattern that will serve as an etch mask in subsequent anisotropic steps for transferring the resist pattern into the underlying material layer. Thus, this resist trim process enables the reduction of the critical dimension of the gate electrode to a size that is well beyond the wavelength of the photolithography.
It is, however, of great importance to accurately control the resist trim process so as to form a precisely defined mask for the subsequent anisotropic etch process for patterning the gate layer stack, since any variation of the gate length directly translates into a corresponding variation of operating speed of the final device. Since the continuous device scaling requires extending the concept of resist trimming even further to obtain the desired reduced critical dimension for a given exposure wavelength, the resist layer thickness has to be adapted to the increased resist material removal during the trim process, thereby significantly deteriorating the optical characteristics of the layer stack comprised of the resist and the bottom anti-reflective coating (ARC). Particularly the reflectivity of the bottom ARC significantly affects the line width after the lithography and causes variations thereof that may not be efficiently compensated for by the subsequent trim process within the tight process tolerances dictated by the design rules.
For this reason, a process technique has recently been developed that proposes the formation of an amorphous carbon layer in combination with a dielectric cap layer as a bottom ARC, thereby providing significantly enhanced control of the reflectivity. Additionally, the carbon/cap layer stack may readily be patterned corresponding to the trimmed resist feature with a reduced resist layer thickness, thereby forming a hard mask feature in the carbon/cap layer stack that is used to etch the polysilicon layer.
With reference to FIGS. 1a-1c, a typical conventional process flow for forming a gate electrode of a field effect transistor on the basis of a carbon/cap layer stack is described in more detail.
FIG. 1a schematically shows a cross-sectional view of a semiconductor device 100 prior to patterning of a material layer on the basis of an advanced photolithography process using a wavelength of 248 nm or 193 nm and on the basis of an advanced etch process with the aid of a hard mask that, in turn, is patterned by a resist mask feature, which is trimmed by a corresponding resist trim process.
The semiconductor device 100 comprises a substrate 101, for instance a silicon substrate or a silicon-on-insulator (SOI) substrate having formed thereon the material layer to be patterned, such as a gate layer stack 102 including a gate insulation layer 103 and a polysilicon layer 104. An amorphous carbon layer 105 is formed on the polysilicon layer 104, followed by a cap layer 106, which may conventionally be comprised of silicon dioxide, silicon oxynitride, nitrogen-free dielectric layers, and the like, wherein silicon oxynitride may be used due to its capability of adjusting the optical characteristics by varying the oxygen/nitrogen ratio. The amorphous carbon layer 105 and the cap layer 106 are designed in such a manner that they act in combination as an efficient anti-reflective coating for the specified exposure wavelength and for the type of resist used. As previously discussed, the reflectivity of an anti-reflective coating during the patterning of a polysilicon layer may significantly affect the accuracy of the resist trim process, thereby also influencing the finally-obtained gate length of the polysilicon feature. For a gate length of 50 nm or less, a deviation of less than one nanometer is mandatory to meet the device specifications. Hence, a high degree of uniformity of the reflectivity provided by the anti-reflective coating formed by the layers 106 and 105 across the entire substrate 101 as well as from substrate to substrate is required so as to reduce the variations in size of a resist mask feature 107 having an initial lateral size 108 and an initial height 109.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. First, the gate layer stack 102 is formed, wherein the gate insulation layer 103 may be formed by advanced oxidation and/or deposition processes so as to obtain the required thickness and material composition for a gate dielectric. Subsequently, the polysilicon layer 104 may be deposited by low pressure chemical vapor deposition (LPCVD) in conformity with well-established process recipes. Thereafter, the amorphous carbon layer 105 is deposited by plasma enhanced CVD from appropriate precursors, wherein a thickness of the layer 105 is adjusted in view of its optical characteristics as well as in view of its etch selectivity during a subsequent anisotropic etch process for patterning the polysilicon layer 104.
Next, the cap layer 106, for instance comprised of silicon oxynitride, may be deposited by PECVD, wherein the thickness and the material composition of the cap layer 106 is selected so as to provide the required phase shifting of the specified exposure wavelength, thereby reducing, in combination with the amorphous carbon layer 105, the back reflection of exposure radiation during the lithography exposure.
Thereafter, a layer of photoresist is deposited, the characteristics of which are adapted to the specified exposure wavelength used during the lithography process, wherein a thickness of the resist layer substantially corresponds to the initial height 109 of the resist mask feature 107, except for a certain degree of shrinkage during any pre- and post-exposure bake processes. To accomplish a high resolution of the lithography process owing to a given depth of focus, it is necessary to provide the resist layer with a thickness of approximately 100-300 nm, depending on the exposure wavelength used. The size reduction of the resist mask feature 107A, depicted in dashed lines, after exposure and development of the resist layer from the initial lateral size 108 to a desired final lateral size 108A, however, is accompanied by a corresponding reduction of the initial height 109 to a final height 109A. The final height 109A may not be sufficient to serve as an etch mask for patterning the polysilicon layer 104 directly, which is a typical process flow for semiconductor devices requiring a gate length on the order of approximately 80-100 nm. For this reason, the amorphous carbon layer 105 is provided and may readily be patterned by reactive ion etching, wherein the final height 109A of the resist mask feature 107, after being subjected to a resist trim process so as to become the reduced resist mask feature 107A, is sufficient to allow reliable patterning of the amorphous carbon layer 105 and the cap layer 106. The cap layer 106 is necessary for substantially avoiding direct contact of the resist layer with the underlying amorphous carbon layer 105, which may otherwise result in resist poisoning and an increased defect rate of the finally obtained polysilicon feature. The reason for this may be chemical reaction between the carbon and the photoresist at the interface thereof, thereby possibly altering the optical characteristics of the photoresist and causing insufficiently developed resist portions that may then be patterned into the polysilicon line 104.
FIG. 1b schematically shows the semiconductor device 100 after completion of the resist trim process and the subsequent reactive ion etching so as to form a hard mask comprised of the residue 105A of the carbon layer 105 and the residue 106A of the cap layer 106 by means of the reduced resist mask feature 107A. Thereafter, the reduced resist mask feature 107A may be removed prior to anisotropically etching the polysilicon layer 104, wherein the thin cap layer residue 106A may also be consumed, while the amorphous carbon layer residue 105A provides the required etch selectivity and allows transfer of the lateral dimension 108A into the polysilicon layer 104.
FIG. 1c schematically shows the semiconductor device 100 after completion of the anisotropic etch process, thereby forming a polysilicon feature 104A substantially exhibiting the lateral size 108A. Although the process flow illustrated above allows formation of polysilicon features 104A having a lateral size 108A of 50 nm and less, it turns out, however, that a moderately high defect rate of the polysilicon features 104A is observed. Correspondingly performed investigations seem to indicate that the defect rate is correlated with the type of cap layer 106 used for defining the hard mask 105A. For instance, a cap layer 106 comprised of silicon oyxnitride exhibits a significant defect rate, thereby rendering the formation process unreliable, while the provision of a cap layer 106 in the form of a silicon dioxide may have the potential to reduce the defect rate, wherein a corresponding conventional deposition process may not be controlled in a reliable manner according to presently available process recipes.
In view of the problems identified above, there is a need for an improved process for forming a cap layer for patterning polysilicon features by means of a carbon hard mask, wherein a defect rate is reduced and process reliability is enhanced.